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LTC1705 1 descriptio u features applicatio s u typical applicatio u the ltc ? 1705 is a complete power supply controller for intel mobile pentium processors. it includes two switch- ing regulator controllers, each designed to drive a pair of n-channel mosfets in a voltage mode feedback, syn- chronous buck configuration, to provide the core and i/o supplies. the core controller includes a 5-bit dac that conforms to the intel mobile vid specification. the ic also includes a low dropout linear regulator (ldo) that delivers up to 150ma of output current to provide the clk supply. the LTC1705 uses a constant-frequency 550khz pwm architecture, minimizing external component size and cost, as well as optimizing load transient performance. it provides better than 1.25% dc accuracy at its core output, and 2% at i/0 and clk outputs. the high performance feedback loops allow the circuit to keep total output regulation within 5% under all transient conditions. an open-drain pgood flag indicates that all three outputs are within 10% of their regulated values. a shutdown circuit disables all three outputs if the run/ss pin is pulled to ground. in this mode, the LTC1705 supply current drops to below 100 m a. n complete power supply controller for intel mobile pentium ? processors n intel mobile pentium core, i/o, clock supplies n multiple logic supply generator , ltc and lt are registered trademarks of linear technology corporation. n three regulated outputs: core, i/o and clk in one package n integrated intel mobile 5-bit vid dac n no external current sense resistors n all n-channel external mosfet architecture n 550khz switching frequency minimizes external component size and cost n integrated 150ma ldo linear regulator n excellent dc accuracy: 1.25% for core, 2% for i/o and clk supplies n pgood flag monitors all three outputs n high efficiency over wide load current range n low shutdown current: < 100 m a n switchers run out-of-phase to minimize c in n small 28-pin narrow ssop package dual 550khz synchronous switching regulator controller with 5-bit vid and 150ma ldo pentium is a registered trademark of intel corporation. intel mobile pentium vrm supply swc bgc i maxc 6 4 8 sensec 13 r imaxc , 27k c outc 180 f 4v 6 l c 0.68 h qbca qbio qbcb pv cc pgood LTC1705 vid4:0 5-bit vid v cc tgc 5 22219 boostc 3 + c outio 100 f 10v 2 + c in 330 f 10v 3 1 f v in 5v v outc 0.9v to 2v 15a + qtcb qtio c cpc 1 f d cpc mbr 0520lt1 qtca r imaxi0 , 16k l io 3 h v outio 1.5v 3a v outclk 2.5v 150ma fbc 11 r31 1.8k r21, 11k compc 10 r pgood 5k c cpio 1 f d cpio mbr 0520lt1 10 10 f c31 1800pf 1 f c voutclk 10 f 10v c vinclk 10 f 10v 1 f 1705 ta01 + c11 1800pf c21 330pf c22 100pf 1 f c12 2200pf rb2 10k 1% run/ss 9 pgnd 7 c ss 0.1 f 10k shutdown c in : kemet t510x337k010as c outc : panasonic eefue0g181r c outio : avx tps0107m010r0065 l c : sumida cep125-4712-t007 l io : sumida cdrh6d28-3r0 qtca, qtcb, qbca, qbcb: fairchild fds6670a qtio, qbio: 1/2 fairchild nds8926 v inclk 3.3v + gnd 12 14?8 swio bgio i maxio 25 28 1 compio 21 tgio 26 boostio 27 fbio 20 v inclk 24 v outclk 23 r22, 11k r12 8.87k 1% +
LTC1705 2 supply voltage v cc , pv cc , v inclk .................................................. 6v boostc, boostio ............................................. 12v boostc C swc, boostio C swio ....................... 6v input voltage swc, swio ................................................ C1v to 6v sensec, fbc, fbio, vid n ....... C 0.3v to (v cc + 0.3v) pgood, run/ss, i maxc , i maxio .................................. C 0.3v to (v cc + 0.3v) peak output current <10 m s tgc, bgc .............................................................. 5a tgio, bgio ....................................................... 1.25a operating temperature range (note 2) .. C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number t jmax = 125 c, q ja = 80 c/w consult ltc marketing for parts specified with wider operating temperature ranges. LTC1705egn absolute axi u rati gs w ww u package/order i for atio uu w electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = pv cc = boost = 5v, v inclk = 3.3v unless otherwise specified. (note 3) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view gn package 28-lead plastic ssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 i maxio pv cc boostc bgc tgc swc pgnd i maxc run/ss compc fbc gnd sensec vid0 bgio boostio tgio swio v inclk v outclk pgood compio fbio v cc vid4 vid3 vid2 vid1 (note 1) symbol parameter conditions min typ max units v cc v cc supply voltage l 3.15 5 5.5 v pv cc pv cc supply voltage (note 4) l 3.15 5 5.5 v bv cc boost pin voltage v boost C v sw (note 4) l 3.15 5 5.5 v v inclk v inclk supply voltage l 3 3.3 5.5 v i vcc v cc supply current test circuit 1 l 4.5 8 ma run/ss = 0v l 40 100 m a i pvcc pv cc supply current v sensec = v fbio = 0v, no load at drivers (note 5) l 26 ma run/ss = 0v (note 6) l 150 m a i boost i boostc + i boostio v sensec = v fbio = 0v, no load at drivers (note 5) l 26 ma run/ss = 0v (note 6) l 150 m a i vinclk v inclk supply current i voutclk = 0ma l 1 1.5 ma run/ss = 0v l 430 m a v shdn run/ss shutdown threshold v run/ss - (rising edge) l 0.2 0.5 v i ss run/ss source current run/ss = 0v C 3 m a core, i/o supply control loops v sensec output voltage accuracy programmed from 0.9v to 2v l C1.25 1.25 % v fbc core feedback voltage (note 10) 0.800 v v fbio i/o feedback voltage l 0.784 0.800 0.816 v dv fb feedback voltage line regulation v cc = 3.3v to 5.5v l 0.01 0.1 %/v dv out output voltage load regulation (note 7) l C0.2 C0.1 % i fbio i/o feedback input current l 1 m a
LTC1705 3 electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = pv cc = boost = 5v, v inclk = 3.3v unless otherwise specified. (note 3) symbol parameter conditions min typ max units a fb feedback amplifier dc gain l 74 85 db gbw feedback amplifier gain bandwidth product f = 100khz (note 7) 20 mhz i comp feedback amplifier output sink/source current l 3 10 ma v pgood negative power good threshold relative to nominal output voltage l C15 C10 C6 % positive power good threshold l 61015 % a ilim current limit amplifier dc gain l 40 60 db i imax i max source current v imaxc = v imaxio = 0v l C12 C10 C8 m a core, i/o supply switching characteristics f osc oscillator frequency test circuit 1 l 460 550 650 khz f osc core and i/o oscillator phase difference (note 7) 180 deg dc max maximum duty cycle l 87 90 93 % t nov driver nonoverlap test circuit 1, 50% to 50% l 10 25 120 ns t r , t f driver rise/fall time test circuit 1, 10% to 90% l 15 100 ns clock supply output v outclk clk output voltage i voutclk = 0ma l 2.45 2.50 2.55 v dv outclk output voltage line regulation v inclk = 3.0v to 5.5v l 0.02 0.1 %/v output voltage load regulation i voutclk = 0ma to 150ma l C 0.1 C 0.05 % ilm clk clk output short-circuit current i voutclk = 0v l C 240 C150 ma v dropout clk output dropout voltage i voutclk = 150ma, d voutclk = C1% (note 8) l 0.3 0.5 v v pgood negative v outclk power good threshold relative to v outclk l C15 C10 C6 % positive v outclk power good threshold relative to v outclk l 61015 % vid inputs r1 resistance across sensec and fbc 10 k w r vid vid input pull-up resistance (note 9) 30 k w v vid vid input threshold l 0.4 1.6 v pgood i pgood v pgood sink current power good l 10 m a power bad l 10 ma v olpg pgood output low voltage i pgood = 1ma l 0.03 0.1 v t pgood v pgood falling edge delay l 248 m s v pgood rising edge delay l 10 20 40 m s v pbad pulse vid code change l 10 20 40 m s note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: the LTC1705 is guaranteed to meet performance specifications from 0 c to 70 c. specifications over the C 40 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 3: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to ground unless otherwise specified. note 4: pv cc and bv cc (v boost C v sw ) must be greater than v gs(on) of the external mosfets to ensure proper operation. note 5: supply current in normal operation is dominated by the current needed to charge and discharge the capacitance of the external mosfet gates. this current varies with supply voltage and the choice of external mosfets. note 6: supply current in shutdown is dominated by external mosfet leakage and may be significantly higher than the quiescent current drawn by the LTC1705, especially at elevated temperature. note 7: guaranteed by design, not subject to test. note 8: dropout voltage is the minimum input-to-output voltage differential required to maintain regulation at the specified output current. in dropout, the output voltage will be equal to v inclk C v dropout . note 9: each internal pull-up resistor attached to the vid inputs has a series diode connected to v cc to allow input voltages higher than the v cc supply without damage or clamping. (see block diagram.) note 10: the core feedback voltage accuracy is guaranteed by the v sense output voltage accuracy test.
LTC1705 4 temperature ( c) 50 25 0 25 50 75 100 125 v sensec (v) 1705 g01 1.315 1.310 1.305 1.300 1.295 1.290 1.285 v cc = 5v v out = 1.3v v cc (v) 3 3.5 4 4.5 5 5.5 6 ? v sensec (mv) 1705 g02 1.30 1.04 0.78 0.52 0.26 0 0.26 0.52 0.78 1.04 1.30 ? v sense (%) 0.10 0.08 0.06 0.04 0.02 0 0.02 0.04 0.06 0.08 0.10 t a = 25 c i load (a) 0 3 6 9 12 15 ? v sensec (mv) 1705 g03 0.8 0 0.8 1.6 2.4 3.2 ? v sense (%) 0.05 0 0.05 0.10 0.15 0.20 t a = 25 c v out = 1.6v i load (a) 0 3 6 9 12 15 efficiency (%) 1705 g04 100 90 80 70 60 50 v in = 5v, t a = 25 c, i/o disabled qtc = qbc = 2 fds6670a v out = 2v v out = 1.6v v out = 0.9v temperature ( c) 50 25 0 25 50 75 100 125 v fbio (v) 1705 g05 0.810 0.806 0.802 0.798 0.794 0.790 v cc = 5v v cc (v) 3 3.5 4 4.5 5 5.5 6 ? v fbio (mv) 1705 g06 0.80 0.64 0.48 0.32 0.16 0 0.16 0.32 0.48 0.64 0.80 ? v fbio (%) 0.10 0.08 0.06 0.04 0.02 0 0.02 0.04 0.06 0.08 0.10 t a = 25 c typical perfor a ce characteristics uw v sensec vs temperature v sensec line regulation v sensec load regulation core supply efficiency v fbio vs temperature v fbio line regulation
LTC1705 5 i load (a) 0 0.5 1 1.5 2 2.5 efficiency (%) 1705 g07 100 90 80 70 60 50 v in = 5v, v out = 1.5v, t a = 25 c, core disabled, qtio = qbio = nds8926 temperature ( c) 50 25 0 25 50 75 100 125 current limit threshold (a) 1705 g09 24 22 20 18 16 14 12 10 v in = 5v, v out = 1.6v, ? v out = 1%, r imaxc = 24.9k, qtc = qbc = 2 fds6670a load current (a) 0 4 8 12 16 20 v outc (v) 1705 g10 2.0 1.5 1.0 0.5 0 t a = 25 c, v in = 5v, v out = 1.6v, qbc = 2 fds6670a, r imaxc = 24.9k, c runss = 0.01 f temperature ( c) 50 25 0 25 50 75 100 125 v outclk (v) 1705 g11 2.55 2.54 2.53 2.52 2.51 2.50 2.49 2.48 2.47 2.46 2.45 v inclk = 3.3v v inclk (v) 3 3.5 4 4.5 5 5.5 6 ? v outclk (mv) 1705 g12 2.5 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 2.5 ? v outclk (%) 0.10 0.08 0.06 0.04 0.02 0 0.02 0.04 0.06 0.08 0.10 t a = 25 c ? v outclk (mv) 1705 g13 0.5 0 0.5 1.0 1.5 2.0 2.5 ? v outclk (%) 0.02 0 0.02 0.04 0.06 0.08 0.10 i outclk (ma) 150 125 100 ?5 ?0 ?5 0 t a = 25 c temperature ( c) 50 25 0 25 50 75 100 125 v dropout (mv) 1705 g14 500 450 400 350 300 250 200 150 100 i outclk = 150ma temperature ( c) 50 25 0 25 50 75 100 125 ilm clk (ma) 1705 g15 150 190 230 270 310 350 v inclk = 3.3v typical perfor a ce characteristics uw i/o supply efficiency v outc 0a to 10a load step current limit threshold vs temperature 0a to 10a load 5a/div v out = 1.6v ac 50mv/ div 5ms/div 1705 g08 v outc vs load current v outclk vs temperature v outclk line regulation v outclk load regulation v outclk dropout voltage vs temperature v outclk short-circuit current vs temperature
LTC1705 6 f osc (khz) 1705 g20 650 610 570 530 490 450 v cc (v) 3 3.5 4 4.5 5 5.5 6 t a = 25 c temperature ( c) 50 25 0 25 50 75 100 125 i imax ( a) 1705 g21 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 v cc = 5v i imax ( a) 1705 g22 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 t a = 25 c v cc (v) 3 3.5 4 4.5 5 5.5 6 temperature ( c) 50 25 0 25 50 75 100 125 vid input threshold (v) 1705 g23 1.6 1.4 1.2 1.0 0.8 0.6 0.4 v cc = 5v vid input threshold (v) 1705 g24 1.6 1.4 1.2 1.0 0.8 0.6 0.4 v cc (v) 3 3.5 4 4.5 5 5.5 6 t a = 25 c temperature ( c) 50 25 0 25 50 75 100 125 supply current (ma) 1705 g25 6.0 4.5 3.0 1.5 0 v cc = pv cc = bv cc = 5v, v inclk = 3.3v, tgc, bgc, tgio, bgio float i vcc i pvcc , i boost i vinclk typical perfor a ce characteristics uw f osc vs v cc i imax vs temperature i imax vs v cc vid input threshold vs temperature vid input threshold vs v cc supply current vs temperature ilm clk (ma) 1705 g16 150 190 230 270 310 350 v inclk (v) 3 3.5 4 4.5 5 5.5 6 t a = 25 c temperature ( c) 50 25 0 25 50 75 100 125 f osc (khz) 1705 g19 650 630 610 590 570 550 530 510 490 470 450 v cc = 5v v outclk short-circuit current vs v inclk v outclk 10ma to 150ma load step f osc vs temperature v outclk ac 5mv/div 10ma to 150ma load 100ma/div 2ms/div 1705 g18.tif
LTC1705 7 i maxio (pin 1): i/o supply current limit set. the i maxio pin sets the current limit comparator threshold for the i/o controller. if the voltage drop across the bottom mosfet, qbio, exceeds the magnitude of the voltage at i maxio , the i/o controller enters current limit. the i maxio pin has an internal 10 m a current source pull-up, allowing the current threshold to be set with a single external resistor to pgnd. kelvin connect this current setting resistor to the source of qbio. refer to the current limit programming section for more information on choosing the value of r imax . pv cc (pin 2): driver power supply input. pv cc provides power to the bgc and bgio output drivers. pv cc must be connected to a voltage high enough to fully turn on the external mosfets qbc and qbio. pv cc should generally be connected directly to v in , the main system 5v supply. pv cc requires at least a 10 m f bypass capacitor directly to pgnd. boostc (pin 3): core controller top gate driver supply. the boostc pin supplies power to the floating tgc driver. bypass boostc to swc with a 1 m f capacitor. an external schottky diode from v in to boostc creates a complete floating charge-pumped supply at boostc. no other external supplies are required. pi fu ctio s uuu bgc (pin 4): core supply bottom gate drive. the bgc pin drives the gate of the bottom n-channel synchronous switch mosfet, qbc. bgc is designed to typically drive up to 10,000pf of gate capacitance. if run/ss goes low, bgc goes low, turning off qbc. tgc (pin 5): core supply top gate drive. the tgc pin drives the gate of the top n-channel mosfet, qtc. the tgc driver draws power from the boostc pin and returns it to the swc pin, providing true floating drive to qtc. tgc is designed to typically drive up to 10,000pf of gate capacitance. if run/ss goes low, tgc goes low, turning off qtc. swc (pin 6): core supply switching node. connect swc to the switching node of the core converter. the tgc driver ground returns to swc, providing floating gate drive to the top n-channel mosfet switch, qtc. the voltage at swc is compared to i maxc by the current limit comparator while the bottom mosfet, qbc, is on. pgnd (pin 7): power ground. the bgc and bgio drivers return to this pin. connect pgnd to a high-current ground node in close proximity to the sources of external mosfets qbc and qbio, and the v in and v out bypass capacitors. i maxc (pin 8): core supply current limit set. see i maxio . tg, bg load (pf) 0 2000 4000 6000 8000 10000 i/o i pvcc , i boost (ma) 1705 g26 12 10 8 6 4 2 0 core i pvcc , i boost (ma) 36 30 24 18 12 6 0 t a = 25 c, pvcc = boost = 5v core drivers supply current with i/o disabled i/o drivers supply current with core disabled tg, bg load (pf) 0 2000 4000 6000 8000 10000 t r , t f (ns) 1705 g27 60 50 40 30 20 10 0 t a = 25 c, pvcc = boost = 5v core drivers i/o drivers temperature ( c) 50 25 0 25 50 75 100 125 v shdn (v) 1705 g28 0.80 0.68 0.56 0.44 0.32 0.20 v cc = 5v measured at run/ss i pvcc , i boost vs driver load drivers rise and fall time vs load v shdn vs temperature typical perfor a ce characteristics uw
LTC1705 8 run/ss (pin 9): softstart. pulling run/ss to gnd exter- nally shuts down the LTC1705 and turns off all the external mosfet switches. the quiescent supply current drops below 100 m a. a capacitor from run/ss to gnd controls the turn on time and rate of rise of the core and i/o output voltages at power up. an internal 3 m a current source pull- up at run/ss sets the turn-on time at approximately 300ms/ m f. compc (pin 10): core controller loop compensation. the compc pin is connected directly to the output of the core controllers error amplifier and the input of the pwm comparator. use an rc network between the compc pin and the fbc pin to compensate the feedback loop for optimum transient response. fbc (pin 11): core controller feedback input. connect the loop compensation network for the core controller to fbc. fbc internally connects to the vid resistor network to set the core output voltage. gnd (pin 12): signal ground. all internal low power circuitry returns to the gnd pin. connect to a low imped- ance ground, separated from the pgnd node. all feed- back, compensation and softstart connections should return to gnd. gnd and pgnd should connect only at a single point, near the pgnd pin and the negative plate of the v in bypass capacitor. sensec (pin 13): core controller output sense. connect to v outc . vid0 to vid4 (pins 14 to 18): vid programming inputs. these are logic inputs that set the output voltage at the core supply to a preprogrammed value (see table 1). vid4 is the msb, vid0 is the lsb. the codes selected by the vid inputs correspond to the intel mobile vid specification. any vid code transition forces pgood to go low for 20 m s. each vid pin includes an on-chip 30k pull-up resistor in series with a diode (see block diagram). v cc (pin 19): power supply input. all internal circuits except the output drivers are powered from this pin. connect v cc to a low-noise 5v supply and bypass the pin to gnd with at least a 10 m f capacitor in close proximity to the LTC1705. pi fu ctio s uuu fbio (pin 20): i/o controller feedback input. connect fbio through a resistor divider network to v outio to set the output voltage. also, connect the loop compensation network for the i/o controller to fbio. compio (pin 21): i/o controller loop compensation. see compc. pgood (pin 22): power good. pgood is an open-drain logic output. pgood pulls low if any of the three supply outputs are out of regulation (see electrical characteris- tics table for core, i/o and clk thresholds). an external pull-up resistor is required at pgood to allow it to swing positive. v outclk (pin 23): clock supply output. v outclk is the output node of the internal linear clock supply regulator. v outclk provides up to 150ma at the 2.5v output to power the cpu clk supply. bypass v outclk with at least a 2.2 m f capacitor to gnd (refer to the v clk linear regulator section). if run/ss goes low, the v outclk regulator shuts down. v inclk (pin 24): clock supply input. v inclk is the input terminal to the internal linear clk supply regulator. con- nect v inclk to a 3.3v supply to maximize efficiency. v inclk can be connected to the 5v supply, but the efficiency of the v outclk regulator is reduced. bypass v inclk with a 10 m f capacitor to gnd. swio (pin 25): i/o controller switching node. see swc. tgio (pin 26): i/o controller top gate drive. see tgc. tgio is designed to typically drive up to 2,000pf of gate capacitance. boostio (pin 27): i/o controller top gate driver power. see boostc. bgio (pin 28): i/o controller bottom gate drive. see bgc. bgio is designed to typically drive up to 2,000pf of gate capacitance.
LTC1705 9 block diagra w io soft- start io driver logic ilmio 10 a pwrgd delay osc 550khz 0.72v 0.88v 0.8v 0.76v 0.84v pv cc 1.08v 1.2v 1.32v core soft- start bandgap reference core driver logic 0.72v 0.88v v cc 0.76v 0.84v pv cc 0.8v r b r1 10k 10k 30k mpg power down entire chip pwrbad io pwrbad core pwrbad clk 0.5v 30k to internal circuitry 30k 30k 30k 10 a fbc minio maxio maxc minc fbio ppgio npgio ppgclk npgclk amp ppgc npgc scmp pwmc pwmio ilmc i maxc boostc pgood run/ss tgc swc bgc compc fbc sensec i maxio boostio tgio swio bgio compio fbio v inclk v outclk 1705 bd pv cc pgnd vid0 vid1 vid2 vid3 vid4 gnd v cc 3 a 2 19 9 22 1 27 26 25 28 20 21 24 23 12 7 18 17 16 15 14 13 11 10 4 6 5 3 8 + + +
LTC1705 10 table 1. vid inputs and corresponding core output voltages code vid4 vid3 vid2 vid1 vid0 v outc 00000 gnd gnd gnd gnd gnd 2.00v 00001 gnd gnd gnd gnd float 1.95v 00010 gnd gnd gnd float gnd 1.90v 00011 gnd gnd gnd float float 1.85v 00100 gnd gnd float gnd gnd 1.80v 00101 gnd gnd float gnd float 1.75v 00110 gnd gnd float float gnd 1.70v 00111 gnd gnd float float float 1.65v 01000 gnd float gnd gnd gnd 1.60v 01001 gnd float gnd gnd float 1.55v 01010 gnd float gnd float gnd 1.50v 01011 gnd float gnd float float 1.45v 01100 gnd float float gnd gnd 1.40v 01101 gnd float float gnd float 1.35v 01110 gnd float float float gnd 1.30v 01111 * gnd float float float float 1.25v v id progra i g codes w uw 10000 float gnd gnd gnd gnd 1.275v 10001 float gnd gnd gnd float 1.250v 10010 float gnd gnd float gnd 1.225v 10011 float gnd gnd float float 1.200v 10100 float gnd float gnd gnd 1.175v 10101 float gnd float gnd float 1.150v 10110 float gnd float float gnd 1.125v 10111 float gnd float float float 1.100v 11000 float float gnd gnd gnd 1.075v 11001 float float gnd gnd float 1.050v 11010 float float gnd float gnd 1.025v 11011 float float gnd float float 1.000v 11100 float float float gnd gnd 0.975v 11101 float float float gnd float 0.950v 11110 float float float float gnd 0.925v 11111 * float float float float float 0.900v *01111 and 11111 are defined by intel to signify no cpu. the LTC1705 generates the output voltages shown if these codes are selected. code vid4 vid3 vid2 vid1 vid0 v outc bgc i maxc compc fbc v fbc v cc pv cc LTC1705 swc pgnd gnd swio v inclk sensec boostc tgc 1705 tc vido:4 run/ss run/ss bgio i maxio compio fbio v fbio v outclk boostio i vinclk i boostio i boostc i pvcc i vcc 5v tgio pgood v outclk 2k 2k 0.1 f 100 f + 10 f + 1000pf 1000pf 2000pf 2000pf f oscio f oscc test circuit 1 test circuit
LTC1705 11 applicatio s i for atio wu u u the LTC1705 includes two, step-down (buck), voltage mode feedback switching regulator controllers and a low dropout linear regulator. the three outputs are designed to power the core, i/o and clk supplies of an intel mobile pentium system. each switching regulator controller em- ploys a synchronous switching architecture with two external n-channel mosfets per channel. the chip oper- ates from a low voltage input supply (6v maximum) and provides high power, high efficiency, precisely regulated output voltages. several features make the LTC1705 par- ticularly suited for microprocessor supply regulation. output regulation at the core supply is extremely tight, with initial accuracy and dc line and load regulation better than 1.25%. total regulation including transient response is inside of 3.5% with a properly designed circuit. the 550khz switching frequency and the high speed internal feedback amplifiers allow the use of physically small, low value external components without compromising perfor- mance. an onboard 5-bit dac sets the core output voltage, consistent with the intel mobile vid specification (table 1). the 800mv internal reference allows regulated output voltages as low as 800mv without external level shifting amplifiers. the linear regulator controls an internal p- channel mosfet that can provide more than 150ma of current at an output voltage of 2.5v. a power good (pgood) flag goes high when all the three outputs are in regulation. 2-step conversion 2-step architectures use a primary regulator to convert the input power source (batteries or ac line voltage) to an intermediate supply voltage, often 5v. this intermediate voltage is then converted to the low voltage, high current supplies required by the system using a secondary regula- tor, such as the LTC1705. 2-step conversion eliminates the need for a single converter to convert a high input voltage to a very low output voltage, often an awkward design challenge. it also fits naturally into systems that continue to use the 5v supply to power portions of their circuitry or have excess 5v capacity available as newer circuit designs shift the current load to lower voltage supplies. each regulator in a typical 2-step system maintains a relatively low step-down ratio (5:1 or less), running at high efficiency while maintaining reasonable duty cycle. in contrast, a regulator converting in a single step from a high input voltage to a 1.xv output must operate at a very narrow duty cycle, mandating trade-offs in external com- ponent values while compromising efficiency and tran- sient response. the efficiency loss can exceed that of a 2-step solution. further complicating the calculation is the fact that many systems draw a significant fraction of their total power off the intermediate 5v supply, bypassing the low voltage supply. 2-step solutions using the LTC1705 usually match or exceed the total system efficiency of single-step solutions and provide the additional benefits of improved transient response, reduced pcb area and simplified power trace routing. 2-step regulation can also buy advantages in thermal management. power dissipation in the LTC1705 portion of a 2-step circuit is lower than it would be in a typical 1-step converter, even in cases where the 1-step converter has higher total efficiency than the 2-step system. in a typical microprocessor core supply regulator, for ex- ample, the regulator is usually located directly next to the cpu. in a 1-step design, all of the power dissipated by the core regulator is located next to the already hot cpu, aggravating thermal management. in a 2-step LTC1705 design, a significant percentage of the power lost in the core regulation system happens in the 5v supply, which is usually located away from the cpu. the power lost to heat in the LTC1705 section of the system is relatively low, minimizing the added heat near the cpu. fast transient response the LTC1705 core and i/o supplies use fast 20mhz gbw op amps as error amplifiers. this allows the compensation network to be designed with several poles and zeros in a more flexible configuration than with typical gm feedback amplifiers. the high bandwidth of the amplifier, coupled with the high 550khz switching frequency and the low values of the external inductor and output capacitor, allow very high loop cross-over frequencies. additionally, a typical LTC1705 circuit uses an inductor value on the order of 1 m h, allowing very fast di/dt slew rates. the result is superior transient response compared with conven- tional solutions.
LTC1705 12 applicatio s i for atio wu u u high efficiency the LTC1705 core and i/o supplies use a synchronous step-down (buck) architecture, with two external n-chan- nel mosfets per output. a floating topside driver and a simple external charge pump provide full gate drive to each upper mosfet. the voltage mode feedback loops and mosfet v ds current limit sensing circuits remove the need for external current sense resistors, eliminating external components and the corresponding power losses in the high current paths. properly designed circuits using low gate charge mosfets are capable of efficiencies exceeding 90% over a wide range of output voltages and load currents. vid programming the LTC1705 includes an onboard feedback network that programs the core output voltage in accordance with the intel mobile vid specification (table 1). this network includes a 10k resistor connected between sensec and fbc and a variable value resistor connected between fbc and gnd, with the value set by the digital code present at the vid4:0 pins. connect sensec to v outc to allow the network to monitor the output voltage. no additional feedback components are required to set the output volt- age of the core controller, although loop compensation components are still required. each vid n pin includes an internal 30k pull-up resistor, allowing it to float high if left unconnected. the pull-up resistors connect to v cc through diodes (see block diagram), allowing the vid n pins to be pulled above v cc without damage. note that codes 01111 and 11111, defined by intel to indicate no cpu present, do generate output voltages at v outc (1.25v and 0.9v, respectively). also, note that the i/o and clk outputs on the LTC1705 are not connected to the vid circuitry and work independently from the core controller. linear regulator and thermal shutdown the LTC1705 clk output is an easy to use monolithic ldo. the v inclk pin powers the regulator and an internal p-channel mos transistor provides the output current at the 2.5v output. an external 10 m f capacitor frequency compensates the linear regulator feedback loop. the clk output is short-circuit protected and the built-in thermal shutdown circuit turns off all three regulator outputs should the LTC1705 junction temperature exceed 155 c. switching architecture details the LTC1705 dual switching regulator controller includes two independent regulator channels. the two switching regulator controllers and their corresponding external components act independently of each other with the exception of the common input bypass capacitor. the run/ss and pgood pins also affect both channels. in the following discussions, when a pin is referred to without mentioning which side is involved, that discussion applies equally to both sides. switching architecture each half of the LTC1705 is designed to operate as a synchronous buck converter (figure 1). each channel includes two high power mosfet gate drivers to control external n-channel mosfets qt and qb. the core drivers have 0.5 w output impedances and can carry well over an amp of continuous current with peak currents up to 5a to slew large mosfet gates quickly. the i/o drivers have 2 w output impedances. the external mosfets are connected with the drain of qt attached to the input supply and the source of qt at the switching node sw. qb is the synchro- nous rectifier with its drain at sw and its source at pgnd. sw is connected to one end of the inductor, with the other end connected to v out . the output capacitor is connected from v out to pgnd. when a switching cycle begins, qb is turned off and qt is turned on. sw rises almost immediately to v in and the inductor current begins to increase. when the pwm pulse finishes, qt turns off and one nonoverlap interval later, qb turns on. now sw drops to pgnd and the inductor current decreases. the cycle repeats with the next tick of the master clock. the percentage of time spent in each mode is controlled by the duty cycle of the pwm signal, which in turn is controlled by the feedback amplifier. the master clock runs at a 550khz rate and turns qt on once every 1.8 m s. in a typical application with a 5v input and a 1.5v
LTC1705 13 output, the duty cycle will be set at 1.5/5 ? 100% or 30% by the feedback loop. this will give roughly a 540ns on- time for qt and a 1.26 m s on-time for qb. this constant frequency operation brings with it a couple of benefits. inductor and capacitor values can be chosen with a precise operating frequency in mind and the feed- back loop components can be similarly tightly specified. noise generated by the circuit will always be in a known frequency band with the 550khz frequency designed to leave the 455khz if band free of interference. subharmonic oscillation and slope compensation, common headaches with constant frequency current mode switchers, are absent in voltage mode designs like the LTC1705. during the time that qt is on, its source (the sw pin) is at v in . v in is also the power supply for the LTC1705. how- ever, qt requires v in +v gs(on) at its gate to achieve mini- mum r on . this presents a problem for the LTC1705it needs to generate a gate drive signal at tg higher than its highest supply voltage. to accomplish this, the tg driver runs from floating supplies, with its negative supply attached to sw and its power supply at boost. this allows it to slew up and down with the source of qt. in combination with a simple external charge pump (figure 2), this allows the LTC1705 to completely enhance the gate of qt without requiring an additional, higher supply voltage. the two channels of the LTC1705 run from a common clock, with the phasing chosen to be 180 from the core side to the i/o side. this has the effect of doubling the frequency of the switching pulses seen by the input bypass capacitor, lowering the rms current seen by the capacitor and reducing the value required. feedback amplifier each side of the LTC1705 senses the output voltage at v out with an internal feedback op amp (see block dia- gram). this is a real op amp with a low impedance output, 85db open-loop gain and 20mhz gain bandwidth product. the positive input is connected internally to an 800mv reference, while the negative input is connected to the fb pin. the output is connected to comp, which is in turn connected to the soft-start circuitry and from there to the pwm generator. unlike many regulators that use a resistor divider con- nected to a high impedance feedback input, the LTC1705 is designed to use an inverting summing amplifier topol- ogy with the fb pin configured as a virtual ground. this allows flexibility in choosing pole and zero locations not available with simple gm configurations. in particular, it allows the use of type 3 compensation, which provides a phase boost at the lc pole frequency and significantly improves loop phase margin (see figure 3). note that the core side of the LTC1705 includes r1 and r b internally as part of the vid dac circuitry. applicatio s i for atio wu u u tg sw bg pgnd LTC1705 qt c in qb l + c out 1705 f01 v out v in + tg c cp d cp boost sw bg pgnd pv cc LTC1705 qt c in qb l + c out 1705 f02 v out v in + + fb 0.8v r1 fb v out LTC1705 comp 1705 f03 r3 c3 c2 r b r2 c1 figure 2. floating tg driver supply figure 1. synchronous buck architecture figure 3. "type 3" feedback loop (i/o channel)
LTC1705 14 applicatio s i for atio wu u u min/max comparators two additional feedback loops keep an eye on the main feedback amplifier and step in if the feedback node moves 5% from its nominal 800mv value. the max comparator (see block diagram) activates if fb rises more than 5% above 800mv. it immediately turns the top mosfet (qt) off and the bottom mosfet (qb) on and keeps them that way until fb falls back within 5% of its nominal value. this pulls the output down as fast as possible, preventing damage to the (often expensive) load. if fb rises because the output is shorted to a higher supply, qb will stay on until the short goes away, the higher supply current limits or qb dies trying to save the load. this behavior provides maximum protection against overvoltage fault at the out- put, while allowing the circuit to resume normal operation when the fault is removed. the min comparator (see block diagram) trips if fb is more than 5% below 800mv and immediately forces the switch duty cycle to 90% to bring the output voltage back into range. it releases when fb is within the 5% window. min is disabled when the soft-start or current limit circuits are activethe only two times that the output should legitimately be below its regulated value. notice that the fb pin is the virtual ground node of the feedback amplifier. a typical compensation network does not include local dc feedback around the amplifier, so that the dc level at fb will be an accurate replica of the output voltage, divided down by r1 and r b (figure 3). however, the compensation capacitors will tend to attenuate ac signals at fb, especially with low bandwidth type 1 feedback loops. this can create a situation where the min, max and pgood comparators do not respond immediately to shifts in the output voltage, if they monitor the output at fb. with vid code switching on the fly, this problem is aggravated. to overcome this, a second resistor divider is used (see block diagram) to provide the min, max and pgood comparators with an accurate replica of the output voltage. this ensures that the comparators react rapidly to code changes. for the i/o channel, the output voltage is indepen- dent of vid codes and therefore the change in v out is minimized. maximizing i/o feedback loop bandwidth will minimize these delays and allow min and max to operate properly. see the feedback loop/compensation section. pgood flag the LTC1705 incorporates a power good pin (pgood). pgood is an open-drain output and requires an external pull-up resistor. if all three regulators are typically within 10% of their nominal value, transistor mpg shuts off (see block diagram) and pgood is pulled high by the external pull-up resistor. if any of the three outputs is more than 10% outside the nominal value for more than 4 m s, pgood pulls low, indicating that an output is out of regulation. for pgood to pull high, all three outputs must be in regulation for more than 20 m s. pgood remains active during soft start and current limit. on power up, pgood pulls low. as soon as the run/ss pin rises above the shutdown thresh- old, the three pair of power good comparators take over and control the transistor mpg directly. the 4 m s and 20 m s delay ensure that short output transient glitches, that are successfully caught by the power good comparators, dont cause momentary glitches at the pgood pin. for the core channel, if there is a vid code change, the internal dac responds by switching its output voltage immediately. however, the switching power supply output slew rate is limited by the output filter. if the vid code step change is small, the power good comparator might not register any transition. to acknowledge the code transi- tion command , the LTC1705 forces pgood to pull low for 20 m s once there is a vid code change. after this short interval, the power good comparators decide the pgood status. shutdown/soft-start the run/ss pin performs two functions: if pulled to ground, it shuts down the LTC1705 and it acts as a conventional soft-start pin, enforcing a maximum duty cycle limit proportional to the voltage at run/ss. an internal 3 m a current source pull-up is connected to the run/ss pin, allowing a soft-start ramp to be generated with a single external capacitor to ground. the 3 m a current source is active even if the LTC1705 is shut down, ensur- ing the device will start when any external pull-down at run/ss is released. in shutdown, the LTC1705 enters micropower sleep mode and quiescent current drops typically below 50 m a.
LTC1705 15 applicatio s i for atio wu u u the run/ss pin shuts down the LTC1705 if it falls below 0.5v (figure 4). between 0.5v and about 1v, the LTC1705 wakes up and the duty cycle is kept to a miminum. as the potential at run/ss increases, the duty cycle increases linearly between 1v and 2v, reaching its final value of 90% when run/ss is above 2v. somewhere before this point, the feedback amplifier will assume control of the loop and the output will come into regulation. when run/ss rises to 1v below v cc , the min feedback comparator is enabled and the LTC1705 is in full operation. includes a trimmed 10 m a pull-up, enabling the user to set the voltage at i max with a single resistor, r imax , to ground. the LTC1705 compares the two inputs and begins limiting the output current when the magnitude of the negative voltage at the sw pin is greater than the voltage at i max . when the load current increases abruptly, the voltage feedback loop forces the duty cycle to increase rapidly and the on-time of qb will be small momentarily. the r ds(on) of qb must be low enough to ensure that the sw node is pulled low within the qb on-time for proper current sensing. the current limit detector is connected to an internal gm amplifier that pulls a current from the run/ss pin propor- tional to the difference in voltage magnitudes between the sw and i max pins. the maximum value of this current is 250 m a (typically). it begins to discharge the soft-start capacitor at run/ss, reducing the duty cycle and control- ling the output voltage until the current drops below the limit. the soft-start capacitor needs to move a fair amount before it has any effect on the duty cycle, adding a delay until the current limit takes effect (figure 4). this allows the LTC1705 to experience brief overload conditions with- out affecting the output voltage regulation. the delay also acts as a pole in the current limit loop to enhance loop stability. while the soft-start capacitor is being discharged, the top mosfet must withstand the high power dissipa- tion due to the high current especially if the regulator is powered by a high current supply. larger overloads cause the soft-start capacitor to pull down quickly, protecting the output components from damage. the current limit gm amplifier includes a clamp to prevent it from pulling run/ ss below 0.5v and shutting off the LTC1705. power mosfet r ds(on) varies from mosfet to mosfet, limiting the accuracy obtainable from the LTC1705 current limit loop. additionally, ringing on the sw node due to parasitics can add to the apparent current, causing the loop to engage early. the LTC1705 current limit is de- signed primarily as a disaster prevention, no blow up circuit and is not useful as a precision current regulator. it should typically be set around 50% above the maximum expected normal output current to prevent component tolerances from encroaching on the normal current range. see the current limit programming section for advice on choosing a valve for r imax . figure 4. soft-start operation in start up and current limit 0v v out 5v 4v 2v 1v 0.5v minimum duty cycle 0v 1705 f04 power-down mode LTC1705 enable min comparator enable run/ss controls duty cycle comp controls duty cycle start up normal operation current limit current limit the LTC1705 includes an onboard current limit circuit that limits the maximum output current to a user-programmed level. it works by sensing the voltage drop across qb during the time that qb is on and comparing that voltage to a user-programmed voltage at i max . since qb looks like a low value resistor during its on-time, the voltage drop across it is proportional to the current flowing in it. in a buck converter, the average current in the inductor is equal to the output current. this current also flows through qb during its on-time. thus, by watching the voltage across qb, the LTC1705 can monitor the output current. any time qb is on and the current flowing to the output is reasonably large, the sw node at the drain of qb will be somewhat negative with respect to pgnd. the LTC1705 senses this voltage, inverts it and compares the sensed voltage with a positive voltage at the i max pin. the i max pin
LTC1705 16 external component selection power mosfets getting peak efficiency out of the LTC1705 depends strongly on the external mosfets used. the LTC1705 requires at least two external mosfets per sidemore if one or more of the mosfets are paralleled to lower on-resis- tance. to work efficiently, these mosfets must exhibit low r ds(on) at 5v v gs to minimize resistive power loss while they are conducting current. they must also have low gate charge to minimize transition losses during switching. on the other hand, voltage breakdown require- ments in a typical LTC1705 circuit are pretty tame: the 6v maximum input voltage limits the v ds and v gs the mosfets can see to safe levels for most devices. low r ds(on) r ds(on) calculations are pretty straightforward. r ds(on) is the resistance from the drain to the source of the mosfetwhen the gate is fully on. many mosfets have r ds(on) specified at 4.5v gate drivethis is the right number to use in LTC1705 circuits running from a 5v supply. as current flows through this resistance while the mosfet is on, it generates i 2 r watts of heat, where i is the current flowing (usually equal to the output current) and r is the mosfet r ds(on) . this heat is only generated when the mosfet is on. when it is off, the current is zero and the power lost is also zero (and the other mosfet is busy losing power). this lost power does two things: it subtracts from the power available at the output, costing efficiency, and it makes the mosfet hotterboth bad things. the effect is worst at maximum load when the current in the mosfets and thus the power lost are at a maximum. lowering r ds(on) improves heavy load efficiency at the expense of additional gate charge (usually) and more cost (usually). proper choice of mosfet r ds(on) becomes a trade-off between tolerable efficiency loss, power dissipation and cost. note that while the lost power has a significant effect on system efficiency, it only adds up to a watt or two in a typical LTC1705 circuit, allowing the use of small, surface mount mosfets without heat sinks. gate charge gate charge is amount of charge (essentially, the number of electrons) that the LTC1705 needs to put into the gate of an external mosfet to turn it on. the easiest way to visualize gate charge is to think of it as a capacitance from the gate pin of the mosfet to sw (for qt) or to pgnd (for qb). this capacitance is composed of mosfet channel charge, actual parasitic drain-source capacitance and miller-multiplied gate-drain capacitance, but can be ap- proximated as a single capacitance from gate to source. regardless of where the charge is going, the fact remains that it all has to come out of pv cc to turn the mosfet gate on and when the mosfet is turned back off, that charge all ends up at ground. in the meanwhile, it travels through the LTC1705s gate drivers, heating them up. more power lost! in this case, the power is lost in little bite-sized chunks, one chunk per switch per cycle, with the size of the chunk set by the gate charge of the mosfet. every time the mosfet switches, another chunk is lost. clearly, the faster the clock runs, the more important gate charge becomes as a loss term. old-fashioned switchers that ran at 20khz could pretty much ignore gate charge as a loss term; in the 550khz LTC1705, gate charge loss can be a significant efficiency penalty. gate charge loss can be the dominant loss term at medium load currents, especially with large mosfets. gate charge loss is also the primary cause of power dissipation in the LTC1705 itself. tg charge pump theres another nuance of mosfet drive that the LTC1705 needs to get around. the LTC1705 is designed to use n-channel mosfets for both qt and qb, primarily be- cause n-channel mosfets generally cost less and have lower r ds(on) than similar p-channel mosfets. turning qb on is simple since the source of qb is attached to pgnd; the LTC1705 just switches the bg pin between pgnd and pv cc . driving qt is another matter. the source of qt is connected to sw which rises to pv cc when qt is on. to keep qt on, the LTC1705 must get tg one mosfet v gs(on) above pv cc . it does this by utilizing a floating driver with the negative lead of the driver attached to sw (the source of qt) and the pv cc lead of the driver coming applicatio s i for atio wu u u
LTC1705 17 applicatio s i for atio wu u u out separately at boost. an external 1 m f capacitor (ccp) connected between sw and boost (figure 2) supplies power to boost when sw is high and recharges itself through dcp when sw is low. this simple charge pump keeps the tg driver alive even as it swings well above pv cc . the value of the bootstrap capacitor ccp needs to be at least 100 times that of the total effective gate capacitance of the topside mosfet(s). for very large external mosfets (or multiple mosfets in parallel), ccp may need to be increased beyond the 1 m f value. input supply the bicmos process that allows the LTC1705 to include large mosfet drivers on-chip also limits the maximum input voltage to 6v. this limits the practical maximum input supply to a loosely regulated 5v rail. the LTC1705 operates properly with input supplies down to about 3.3v, so a typical 3.3v supply can also be used if the external mosfets are appropriately chosen (see the power mosfets section). at the same time, the input supply needs to supply several amps of current without excessive voltage drop. the input supply must have regulation adequate to prevent sudden load changes from causing the LTC1705 input voltage to dip. in typical applications where the LTC1705 is generat- ing a secondary low voltage logic supply, all of these input conditions are met by the main system logic supply when fortified with an input bypass capacitor. input bypass capacitor a typical LTC1705 circuit running from a 5v logic supply might provide 1.6v at 15a at its core output. 5v to 1.6v implies a duty cycle of 32%, which means qtc is on 32% of each switching cycle. during qtcs on-time, the current drawn from the input equals the load current and during the rest of the cycle, the current drawn from the input is near zero. this 0a to 15a, 32% duty cycle pulse train adds up to 7a rms at the input. at 550khz, switching cycles last about 1.8 m smost system logic supplies have no hope of regu- lating output current with that kind of speed. a local input bypass capacitor is required to make up the difference and prevent the input supply from dropping drastically when qtc kicks on. this capacitor is usually chosen for rms ripple current capability and esr as well as value. the LTC1705 i/o channel typically operates at a much smaller output current, hence the input bypass capacitor in an LTC1705 circuit should be chosen primarily to meet the core output requirement. consider our 15a example. the input bypass capacitor gets exercised in three ways: its esr must be low enough to keep the initial drop as qt turns on within a reasonable value (100mv or so); its rms current capability must be adequate to withstand the 7a rms ripple current at the input and the capacitance must be large enough to main- tain the input voltage until the input supply can make up the difference. generally, a capacitor that meets the first two parameters will have far more capacitance than is required to keep capacitance-based droop under control. in our example, we need 0.006 w esr to keep the input drop under 100mv with a 15a current step and 7a rms ripple current capacity to avoid overheating the capacitor. these requirements can be met with multiple low esr tantalum or electrolytic capacitors in parallel or with a large monolithic ceramic capacitor. tantalum capacitors are a popular choice as input capaci- tors for LTC1705 applications, but they deserve a special caution here. generic tantalum capacitors have a destruc- tive failure mechanism if they are subjected to large rms currents (like those seen at the input of a LTC1705). at some random time after they are turned on, they can blow up for no apparent reason. the capacitor manufacturers are aware of this and sell special surge tested tantalum capacitors specifically designed for use with switching regulators. when choosing a tantalum input capacitor, make sure that it is rated to carry the rms current that the LTC1705 will draw. if the data sheet doesnt give an rms current rating, chances are the capacitor isnt surge tested. dont use it! output bypass capacitor the output bypass capacitor has quite different require- ments from the input capacitor. the ripple current at the output of a buck regulator like the LTC1705 is much lower than at the input, due to the fact that the inductor current is constantly flowing at the output. the primary concern at the output is capacitor esr. fast load current transitions at the output appear as voltage across the esr of the
LTC1705 18 output bypass capacitor until the feedback loop in the LTC1705 can change the inductor current to match the new load current value. this esr step at the output is often the single largest budget item in the load regulation calculation. as an example, our hypothetical 1.6v, 15a switcher with a 0.006 w esr output capacitor would experience a 90mv step at the output with a 0a to 15a load stepa 5.6% output change! usually the solution is to parallel several capacitors at the output. for example, to keep the transient response in side of 3.5% with the previous design, wed need an output esr better than 0.004 w . this can be met with six 0.025 w , 180 m f special polymer capacitors in parallel. inductor the inductor in a typical LTC1705 circuit is chosen prima- rily for value and saturation current. the inductor value sets the ripple current, which is commonly chosen be- tween 20% to 40% of the anticipated full load current. ripple current is set by: i tv l ripple on qb out = () () in our 1.6v, 15a example, wed set the ripple to 20% of 15a or 3a and the inductor value would be: l tv i sv a h with t v v khz s on qb out ripple on qb == m =m =- ? ? ? ? =m () () () (. )(. ) . . /. 12 16 3 067 1 16 5 550 1 2 the inductor must not saturate at the expected peak current. in this case, if the current limit was set to 22.5a, the inductor should be rated to withstand 22.5a + (0.5 ? i ripple ) or 24a without saturating. feedback loop/compensation feedback loop types in a typical LTC1705 circuit, the feedback loop consists of the modulator, the external inductor, the output capacitor and the feedback amplifier with its compensation network. all of these components affect loop behavior and must be accounted for in the loop compensation. the modulator consists of the internal pwm generator, the output mosfet drivers and the external mosfets themselves. from a feedback loop point of view, it looks like a linear voltage transfer function from comp to sw and has a gain roughly equal to the input voltage. it has fairly benign ac behavior at typical loop compensation frequencies with significant phase shift appearing at half the switching frequency. the external inductor/output capacitor combination makes a more significant contribution to loop behavior. these components cause a second order lc roll off at the output, with the attendant 180 phase shift. this rolloff is what filters the pwm waveform, resulting in the desired dc output voltage, but the phase shift complicates the loop compensation if the gain is still higher than unity at the pole frequency. eventually (usually well above the lc pole frequency), the reactance of the output capacitor will approach its esr and the rolloff due to the capacitor will stop, leaving 6db/octave and 90 of phase shift (figure 5). applicatio s i for atio wu u u gain (db) 1705 f05 a v 0 phase 6db/oct ?2db/oct gain phase (deg) freq ?0 180 270 360 figure 5. transfer function of buck modulator so far, the ac response of the loop is pretty well out of the users control. the modulator is a fundamental piece of the LTC1705 design and the external l and c are usually chosen based on the regulation and load current require- ments without considering the ac loop response. the feedback amplifier, on the other hand, gives us a handle with which to adjust the ac response. the goal is to have 180 phase shift at dc (so the loop regulates) and some- thing less than 360 phase shift at the point that the loop
LTC1705 19 applicatio s i for atio wu u u gain falls to 0db. the simplest strategy is to set up the feedback amplifier as an inverting integrator, with the 0db frequency lower than the lc pole (figure 6). this type 1 configuration is stable but transient response is less than exceptional if the lc pole is at a low frequency. figure 7 shows an improved type 2 circuit that uses an additional pole-zero pair to temporarily remove 90 of phase shift. this allows the loop to remain stable with 90 more phase shift in the lc section, provided the loop reaches 0db gain near the center of the phase bump. type 2 loops work well in systems where the esr zero in the lc roll-off happens close to the lc pole, limiting the total phase shift due to the lc. the additional phase compensation in the feedback amplifier allows the 0db point to be at or above the lc pole frequency, improving loop bandwidth substantially over a simple type 1 loop. it has limited ability to compensate for lc combinations where low capacitor esr keeps the phase shift near 180 for an extended frequency range. LTC1705 circuits using conventional switching grade electrolytic output capaci- tors can often get acceptable phase margin with type 2 compensation. gain (db) 1705 f07 0 phase 6db/oct 6db/oct gain phase (deg) freq ?0 180 270 360 r b v ref r1 r2 fb c2 in out + c1 gain (db) 1705 f08 0 phase 6db/oct +6db/oct 6db/oct gain phase (deg) freq ?0 180 270 360 r b v ref r1 r2 fb c2 in out + c1 c3 r3 gain (db) 1705 f06 0 phase 6db/oct gain phase (deg) freq ?0 180 270 360 r b r1 fb c1 in out + v ref figure 6. type 1 schematic and transfer function figure 7. type 2 schematic and transfer function figure 8. type 3 schematic and transfer function type 3 loops (figure 8) use two poles and two zeros to obtain a 180 phase boost in the middle of the frequency band. a properly designed type 3 circuit can maintain acceptable loop stability even when low output capacitor esr causes the lc section to approach 180 phase shift well above the initial lc roll-off. as with a type 2 circuit, the loop should cross through 0db in the middle of the phase bump to maximize phase margin. many LTC1705 circuits using low esr tantalum or os-con output capaci- tors need type 3 compensation to obtain acceptable phase margin with a high bandwidth feedback loop. feedback component selection selecting the r and c values for a typical type 2 or type 3 loop is a nontrivial task. the applications shown in this data sheet show typical values, optimized for the power components shown. they should give acceptable perfor- mance with similar power components, but can be way off if even one major power component is changed signifi- cantly. applications that require optimized transient re- sponse will need to recalculate the compensation values specifically for the circuit in question. the underlying mathematics are complex, but the component values can be calculated in a straightforward manner if we know the gain and phase of the modulator at the crossover fre- quency. modulator gain and phase can be measured directly from a breadboard or can be simulated if the appropriate parasitic values are known. measurement will give more accurate results, but simulation can often get close enough to give a working system. to measure the modulator gain and phase directly, wire up a breadboard with an LTC1705
LTC1705 20 and the actual mosfets, inductor and input and output capacitors that the final design will use. this breadboard should use appropriate construction techniques for high speed analog circuitry: bypass capacitors located close to the LTC1705, no long wires connecting components, appropriately sized ground returns, etc. wire the feedback amplifier as a simple type 1 loop, with a 10k resistor from v out to fb and a 0.1 m f feedback capacitor from comp to fb. choose the bias resistor (r b ) as required to set the desired output voltage. disconnect r b from ground and connect it to a signal generator or to the source output of a network analyzer (figure 9) to inject a test signal into the loop. measure the gain and phase from the comp pin to the output node at the positive terminal of the output capacitor. make sure the analyzers input is ac coupled so that the dc voltages present at both the comp and v out nodes dont corrupt the measurements or damage the analyzer. *1705 modulator gain/phase *2000 linear technology *this file written to run with pspice 8.0 *may require modifications for other spice simulators *mosfets rfet mod sw 0.02 ;mosfet rdson *inductor lext sw out1 1u ;inductor value rl out1 out 0.005 ;inductor series r *output cap cout out out2 1000u ;capacitor value resr out2 0 0.01 ;capacitor esr *1705 internals emod mod 0 comp 0 5 ;3.3 for 3.3v supply vstim comp 0 0 ac 1 ;ac stimulus .ac dec 100 1k 1meg .probe .end with the gain/phase plot in hand, a loop crossover fre- quency can be chosen. usually the curves look something like figure 5. choose the crossover frequency in the rising or flat parts of the phase curve, beyond the external lc poles. frequencies between 10khz and 50khz usually work well. note the gain (gain, in db) and phase (phase, in degrees) at this point. the desired feedback amplifier gain will be -gain to make the loop gain at 0db at this frequency. now calculate the needed phase boost, assum- ing 60 as a target phase margin: boost = C (phase + 30 ) if the required boost is less than 60 , a type 2 loop can be used successfully, saving two external components. boost values greater than 60 usually require type 3 loops for satisfactory performance. applicatio s i for atio wu u u figure 9. modulator gain/phase measurement set up boost 1 f 0.1 f mbr0530t tg sw bg pgnd pv cc gnd v cc 10 ac source from analyzer LTC1705 10 f qb l + c out 1705 f09 v out to analyzer v comp to analyzer r b 5v + run/ss nc qt fb comp 10k if breadboard measurement is not practical, a spice simulation can be used to generate approximate gain/ phase curves. plug the expected capacitor, inductor and mosfet values into the following spice deck and gener- ate an ac plot of v(v out )/v(comp) in db and phase of v out in degrees. refer to your spice manual for details of how to generate this plot.
LTC1705 21 applicatio s i for atio wu u u finally, choose a convenient resistor value for r1 (10k is usually a good value). now calculate the remaining values: (k is a constant used in the calculations) f = chosen crossover frequency g = 10 (gain/20) (this converts gain in db to g in absolute gain) type 2 loop: k tan boost c fgkr cck r k fc r vr vv b ref out ref =+ ? ? ? ? = =- () = = - 2 45 2 1 21 12 1 2 21 1 2 p p () type 3 loop: k tan boost c fgr cck r k fc r r k c fkr r vr vv b ref out ref =+ ? ? ? ? = =- () = = - = = - 2 4 45 2 1 21 12 1 2 21 3 1 1 3 1 23 1 p p p () current limit programming programming current limit on the LTC1705 is straight- forward. the i max pin sets the current limit by setting the maximum allowable voltage drop across qb (the bottom mosfet) before the current limit circuit engages. the voltage across qb is set by its on-resistance and the current flowing in the inductor, which is the same as the output current. the LTC1705 current limit circuit inverts the negative voltage across qb before comparing it with the voltage at i max , allowing the current limit to be set with a positive voltage. to set the current limit, calculate the expected voltage drop across qb at the maximum desired current: v prog = (i limit ) (r ds(on) ) i limit should be chosen to be quite a bit higher than the expected operating current, to allow for mosfet r ds(on) changes with temperature. setting i limit to 150% of the maximum normal operating current is usually safe and will adequately protect the power components if they are chosen properly. note that the ringing on the switch node can cause error for the current limit threshold. this factor will change depending on the layout and the components used. v prog is then programmed at the i max pin using the internal 10 m a pull-up and an external resistor: r imax = v prog /10 m a the resulting value of r imax should be checked in an actual circuit to ensure that the current circuit kicks in as expected. mosfet r ds(on) specs are like horsepower ratings in automobiles and should be taken with a grain of salt. circuits that use very low values for r imax (<10k) should be checked carefully, since small changes in r imax can cause large i limit changes when the switch node ringing makes up a large percentage of the total v prog value. if v prog is set too low, the LTC1705 may fail to start up.
LTC1705 22 accuracy trade-offs the v ds sensing scheme used in the LTC1705 is not particularly accurate, primarily due to uncertainty in the r ds(on) from mosfet to mosfet. a second error term arises from the ringing present at the sw pin, which causes the v ds to look larger than (i load )(r ds(on) ) at the beginning of qbs on-time. these inaccuracies do not prevent the LTC1705 current limit circuit from protecting itself and the load from damaging overcurrent conditions, but they do prevent the user from setting the current limit to a tight tolerance if more than one copy of the circuit is being built. the 50% factor in the current setting equation above reflects the margin necessary to ensure that the circuit will stay out of current limit at the maximum normal load, even with a hot mosfet that is running quite a bit higher than its r ds(on) spec. v clk linear regulator the LTC1705 monolithic ldo linear regulator is easy to use. input and output supply bypass capacitors are the only two external components required for this ldo. the v inclk pin powers up the regulator and an internal p-channel mos transistor sources at least 150ma of current at a fixed output voltage of 2.5v. this device is short-circuit protected and includes thermal shutdown to turn off all three regulator outputs should the junction temperature exceed about 155 c. the circuit design in the LTC1705 requires the use of an output capacitor as part of the frequency compensation. a minimum output capacitor of 2.2 m f and esr larger than 100m w is recommended to prevent oscillations. larger values of output capacitance decrease the peak deviations and provide improved transient response for large load current changes. many different types of capacitors are available and have widely varying characteristics. these capacitors differ in capacitor tolerance (sometimes rang- ing up to 100%), equivalent series resistance, equivalent series inductance and capacitance temperature coeffi- cient. in a typical operating condition, a 10 m f solid tanta- lum at the v outclk pin ensures stability. the avx tpsd106m035r0300 or equivalent works well in this application. optimizing performance 2-step conversion the LTC1705 is ideally suited for use in 2-step conversion systems. 2-step systems use a primary regulator to con- vert the input power source (batteries or ac line voltage) to an intermediate supply voltage, often 5v. the LTC1705 then converts the intermediate voltage to the lower volt- age, high current supplies required by the system. com- pared to a 1-step converter that converts a high input voltage directly to a very low output voltage, the 2-step converter exhibits superior transient response, smaller component size and equivalent efficiency. thermal man- agement and layout complexity are also improved with a 2-step approach. a typical notebook computer supply might use a 4-cell li- ion battery pack as an input supply with a 15v nominal terminal voltage. the logic circuits require 5v/3a and 3.3v/5a to power system board logic and 2.5v/0.15a, 1.5v/2a and 1.3v/15a to power the cpu. a typical 2-step conversion system would use a step-down switcher (per- haps an ltc1628 or two ltc1625s) to convert 15v to 5v and another to convert 15v to 3.3v (figure 10). the 3.3v input supply can power the 1.3v output at the LTC1705 core channel and the 2.5v ldo. the 5v input supply can power the 1.5v i/o channel. the corresponding 1-step system would use four similar step-down switchers plus an ldo, each switcher using 15v as the input supply and generating one of the four output voltages. clearly, the 5v and 3.3v sections of the two schemes are equivalent. the 2-step system draws additional power from the 5v and 3.3v outputs, but the regulation tech- niques and trade-offs at these outputs are similar. the difference lies in the way the 1.5v and 1.3v supplies are generated. for example, the 2-step system converts 3.3v to 1.3v with a 39% duty cycle. during the qt on-time, the voltage across the inductor is 2v and during the qb on- time, the voltage is 1.3v, giving roughly symmetrical transient response to positive and negative load steps. the 2v maximum voltage across the inductor allows the use of a small 0.47 m h inductor while keeping ripple current to 3a (20% of the 15a maximum load). by contrast, the 1-step applicatio s i for atio wu u u
LTC1705 23 applicatio s i for atio wu u u converter is converting 15v to 1.3v, requiring just a 9% duty cycle. inductor voltages are now 13.7v when qt is on and 1.3v when qb is on, giving vastly different di/dt values and correspondingly skewed transient response with posi- tive and negative current steps. the narrow 9% duty cycle usually requires a lower switching frequency, which in turn requires a higher value inductor and larger output capacitor. parasitic losses due to the large voltage swing at the source of qt cost efficiency, eliminating any advan- tage the 1-step conversion might have had. note that power dissipation in the LTC1705 portion of a 2-step circuit is lower than it would be in a typical 1-step converter, even in cases where the 1-step converter has higher total efficiency than the 2-step system. in a typical microprocessor core supply regulator, for example, the regulator is usually located right next to the cpu. in a 1-step design, all of the power dissipated by the core regulator is right there next to the hot cpu, aggravating thermal management. in a 2-step LTC1705 design, a significant percentage of the power lost in the core regu- lation system happens in the 5v or 3.3v supply, which is usually away from the cpu. the power lost to heat in the LTC1705 section of the system is relatively low, minimiz- ing the heat near the cpu. additionally, with a 1-step converter, the high input battery voltage requires the mosfet to operate at high voltage levels. this imposes stringent requirements on the mosfets selection. most of the mosfets that meet the high voltage and high current requirements are expensive and bulky. this makes for an awkward power supply design, especially in portable applications. the high input voltage also necessitates higher gate drive, which aggra- vate switching losses. figure 10. 2-step conversion block diagram 2-step conversion offers better transient response smaller component size better thermal management lower voltage requirement for mosfets smaller switching loss equivalent efficiency ltc1628* 5v/3a logic supply 1.5v/2a cpu i/o supply 1.3v/15a cpu core supply 3.3v/5a logic supply 2.5v/0.15a cpu clock supply *or two ltc1625s i/o core LTC1705 cpu supply controller ldo 1705 f10
LTC1705 24 2-step efficiency calculation calculating the efficiency of a 2-step converter system involves some subtleties. simply multiplying the effi- ciency of the primary 5v or 3.3v supply by the efficiency of the 1.5v or 1.3v supply under estimates the actual efficiency, since a significant fraction of the total power is drawn from the 3.3v and 5v rails in a typical system. the correct way to calculate system efficiency is to calculate the power lost in each stage of the converter and divide the total output power from all outputs by the sum of the output power plus the power lost: efficiency total output power total output power total output lost = + () 100% in our example 2-step system, the total output power is: total output power = 15w + 16.5w + 0.375w + 3w + 19.5w = 54.375w (corresponding to 5v, 3.3v, 2.5v, 1.5v and 1.3v output voltages) assuming the LTC1705 provides 90% efficiency at the core and i/o channels, and 75% efficiency at the ldo, the additional loads on the 5v and 3.3v supplies are: 1.3v: 19.5w/90% =21.67w t 6.6a from 3.3v 1.5v: 3w/90% =3.3w t 0.66a from 5v 2.5v: 0.375w/75% =0.5w t 0.152a from 3.3v applicatio s i for atio wu u u if the 5v and 3.3v supplies are each 94% efficient, the power lost in each supply is: 1.3v: 21.67w C 19.5w = 2.17w 1.5v: 3.3w C 3w = 0.3w 2.5v: 0.5w C 0.375w = 0.125w 3.3v: 16.5w + 3.3v(6.6a + 0.152a) = 38.78w load (38.78w/94%) C 38.78w = 2.48w lost 5v: 15w + 5v(0.66a) = 18.3w load (18.3w/94%) C 18.3w = 1.17w lost total loss = 6.25w total system efficiency = 54.375w/(54.375w + 6.25w) = 89.7% maximizing high load current efficiency efficiency at high load currents is primarily controlled by the resistance of the components in the power path (qt, qb, l ext ) and power lost in the gate drive circuits due to mosfet gate charge. maximizing efficiency in this region of operation is as simple as minimizing these terms. the behavior of the load over time affects the efficiency strategy. parasitic resistances in the mosfets and the inductor set the maximum output current the circuit can supply without burning up. a typical efficiency curve shows that peak efficiency occurs near 30% of this maxi- mum current. if the load current will vary around the efficiency peak and will spend relatively little time at the maximum load, choosing components so that the average load is at the efficiency peak is a good idea. this puts the maximum load well beyond the efficiency peak, but usu- ally gives the greatest system efficiency over time, which translates to the longest run time in a battery-powered system. if the load is expected to be relatively constant at the maximum level, the components should be chosen so that this load lands at the peak efficiency point, well below the maximum possible output of the converter.
LTC1705 25 applicatio s i for atio wu u u regulation over component tolerance/ temperature dc regulation accuracy the LTC1705 initial dc output accuracy depends mainly on internal reference accuracy, op amp offset and internal or external resistor accuracy. two LTC1705 specs come into play: v sensec voltage and feedback voltage line regu- lation. the v sensec voltage spec is within 1.25% for all vid codes over the full temperature range, which encom- passes reference accuracy, error amplifier offset and the input resistor divider mismatch. the feedback voltage line regulation spec adds an additional 0.1%/v term that accounts for change in reference output with change in input supply voltage. with a 5v supply, the errors contrib- uted by the LTC1705 itself add up to less than 1.5% dc error at the output. at the i/o side, the output voltage setting resistors (r1 and r b in figure 3) are the other major contributor to dc error. at a typical 1.xv output voltage, the resistors are of roughly the same value, which tends to halve their error terms, improving accuracy. still, using 1% resistors for r1 and r b will add 1% to the total output error budget. using 0.1% resistors in just those two positions can nearly halve the dc output error for very little additional cost. load regulation load regulation is affected by feedback amplifier gain and external ground drops in the feedback path. a full-range load step might require a 10% duty cycle change to keep the output constant, requiring the comp pin to move about 100mv. with amplifier gain at 85db, this adds up to only a 10 m v shift at fb, negligible compared to the refer- ence accuracy terms. external ground drops arent so negligible. the LTC1705 can sense the positive end of the output voltage by attaching the feedback resistor directly at the load, but it cannot do the same with the ground lead. just 0.001 w of resistance in the ground lead at 15a load will cause a 15mv error in the output voltageas much as all the other dc errors put together. proper layout becomes essential to achieving optimum load regulation from the LTC1705. a properly laid out LTC1705 circuit should move not more than one to two millivolts at the output from zero to full load. transient response transient response is the other half of the regulation equation. the LTC1705 can keep the dc output voltage constant to within 1% when averaged over hundreds of cycles. over just a few cycles, however, the external components conspire to limit the speed that the output can move. consider our typical 5v to 1.5v circuit, sub- jected to a 1a to 5a load transient. initially, the loop is in regulation and the dc current in the output capacitor is zero. suddenly, an extra 4a start flowing out of the output capacitor while the inductor is still supplying only 1a. this sudden change will generate a (4a)(r esr )voltage step at the output; with a typical 0.015 w output capacitor esr, this is a 60mv or 4% (for a 1.5v output voltage) step at the output! very quickly, the feedback loop will realize that something has changed and will move at the bandwidth allowed by the external compensation network towards a new duty cycle. if the bandwidth is set to 50khz, the comp pin will get to 60% of the way to 90% duty cycle in 3 m s. now the inductor is seeing 3.5v across itself for a large portion of the cycle and its current will increase from 1a at a rate set by di/dt = v/l. if the inductor value is 0.5 m h, the peak di/dt will be 3.5v/0.5 m h or 7a/ m s. sometime in the next few micro-seconds after the switch cycle begins, the inductor current will have risen to the 5a level of the load current and the output voltage will stop dropping. at this point, the inductor current will rise somewhat above the level of the output current to replenish the charge lost from the output capacitor during the load transient. during the next couple of cycles, the min comparator may trip on and off, preventing the output from falling below its -5% threshold until the time constant of the compensation loop runs out and the main feedback amplifier regains control. with a properly compensated loop, the entire recovery time will be inside of 10 m s.
LTC1705 26 typical applicatio s u figure 11. transient load generator most loads care only about the maximum deviation from ideal, which occurs somewhere in the first two cycles after the load step hits. during this time, the output capacitor does all the work until the inductor and control loop regain control. the initial drop (or rise if the load steps down) is entirely controlled by the esr of the capacitor and amounts to most of the total voltage drop. to minimize this drop, reduce the esr as much as possible by choosing low esr capacitors and/or paralleling multiple capacitors at the output. the capacitance value accounts for the rest of the voltage drop until the inductor current rises. with most output capacitors, several devices paralleled to get the esr down will have so much capacitance that this drop term is negligible. ceramic capacitors are an exception; a small ceramic capacitor can have suitably low esr with relatively small values of capacitance, making this second drop term significant. optimizing loop compensation loop compensation has a fundamental impact on tran- sient recovery time, the time it takes the LTC1705 to recover after the output voltage has dropped due to output capacitor esr. optimizing loop compensation entails maintaining the highest possible loop bandwidth while ensuring loop stability. the feedback component selection section describes in detail the techniques used to design an optimized type 3 feedback loop, appropriate for most LTC1705 systems. measurement techniques measuring transient response presents a challenge in two respects: obtaining an accurate measurement and gener- ating a suitable transient to use to test the circuit. output measurements should be taken with a scope probe di- rectly across the output capacitor. proper high frequency probing techniques should be used. in particular, dont use the 6" ground lead that comes with the probe! use an adapter that fits on the tip of the probe and has a short ground clip to ensure that inductance in the ground path LTC1705 v out irfz44 or equivalent r load 50 0v to 10v 100hz, 5% duty cycle locate close to the output 1705 f11 pulse generator doesnt cause a bigger spike than the transient signal being measured. conveniently, the typical probe tip ground clip is spaced just right to span the leads of a typical output capacitor. now that we know how to measure the signal, we need to have something to measure. the ideal situation is to use the actual load for the test and switch it on and off while watching the output. if this isnt convenient, a current step generator is needed. this generator needs to be able to turn on and off in nanoseconds to simulate a typical switching logic load, so stray inductance and long clip leads between the LTC1705 and the transient generator must be minimized. figure 11 shows an example of a simple transient genera- tor. be sure to use a noninductive resistor as the load elementmany power resistors use an inductive spiral pattern and are not suitable for use here. a simple solution is to take ten 1/4w film resistors and wire them in parallel to get the desired value. this gives a noninductive resistive load which can dissipate 2.5w continuously or 50w if pulsed with a 5% duty cycle, enough for most LTC1705 circuits. solder the mosfet and the resistor(s) as close to the output of the LTC1705 circuit as possible and set up the signal generator to pulse at a 100hz rate with a 5% duty cycle. this pulses the LTC1705 with 500 m s transients10ms apart, adequate for viewing the entire transient recovery time for both positive and negative transitions while keep- ing the load resistor cool.
LTC1705 27 package descriptio u information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. gn package 28-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) 0.386 ?0.393* (9.804 ?9.982) gn28 (ssop) 1098 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side 12 3 4 5 6 7 8 9 10 11 12 0.229 ?0.244 (5.817 ?6.198) 0.150 ?0.157** (3.810 ?3.988) 20 21 22 23 24 25 26 27 28 19 18 17 13 14 16 15 0.016 ?0.050 (0.406 ?1.270) 0.015 0.004 (0.38 0.10) 45 0 ?8 typ 0.0075 ?0.0098 (0.191 ?0.249) 0.053 ?0.069 (1.351 ?1.748) 0.008 ?0.012 (0.203 ?0.305) 0.004 ?0.009 (0.102 ?0.249) 0.0250 (0.635) bsc 0.033 (0.838) ref
LTC1705 28 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com ? linear technology corporation 2001 1705fa lt/tp 0801 1.5k rev a ? printed in usa related parts typical applicatio u part number description comments ltc1628/ltc1628-pg dual high efficiency 2-phase synchronous step-down controller constant frequency, standby 5v and 3.3v ldos, 3.5v v in 36v ltc1703 dual 550khz synchronous 2-phase switching regulator mobile vid control with 25mhz gbw voltage mode, v in 7v controller with vid ltc1708 dual, 2-phase synchronous step-down controller with 5-bit vid mobile cpu vid, dual output 3.5v v in 36v, minimum c in and c out ltc1736 synchronous step-down controller with 5-bit vid control output fault protection, power good output, 3.5v to 36v input swc bgc i maxc 6 4 8 sensec 13 27k 180 f 4v 6 l3 0.68 h qb1b qb2 qb1a pv cc vid0 vid0 14 pgood LTC1705 v cc tgc 5 22219 boostc 3 + 100 f 4v 2 + 150 f 6.3v 2 1 f v outc 0.9v to 2v 15a + qt2 1 f d6 mbr0520lt1 qt1a qt1b 16k l4 3 h v outio 1.5v 3a v outclk 2.5v 150ma fbc 11 1.8k 11k compc 10 5k 1 f d7 mbr 0520lt1 10 10 f 1800pf 1 f 1 f 10 f 10v 10 f 10v 1 f 1705 ta02 + 1800pf 330pf 100pf 1 f 2200pf 10k 1% run/ss 9 pgnd 7 0.1 f coreenable q1, q2, q3: irf7805 q4, q5: irf7807 l1: etqp6f2r9l l2: etqp6f4r6h qt1a, qt1b, qb1a, qb1b: fairchild fds6670a qt2, qb2: nds8926 l3: sumida cep125-4712-t007 l4: sumida cdrh6d28-3r0 + gnd 12 swio bgio i maxio 25 28 1 compio 21 tgio 26 boostio 27 fbio 20 v inclk 24 v outclk 23 11k 8.87k 1% sw1 bg1 sense1 + 26 23 2 sense1 3 150 f 6.3v 2 d5 mbrd 835l d4 mbrs 130t3 l1 2.9 h 4m q3 q4 intv cc ltc1628 fltcpl v in v osense1 tg1 27 21 24 boost1 25 l5, 0.33 h d03316p-331hc + c in 22 f 50v 0.1 f 50v v out1 5v 4a stdby5v + q5 0.22 f d1 cmdsh-3 q1 q2 extv cc 22 1 8 9 5 7 28 4 pgnd 1000pf 10 1000pf 0.1 f d2 cmdsh-3 105k 1% 20k 1% 10 0.1 f 50v 1 f 4.7 f + 10 f 6.3v 100pf 47pf 0.1 f 50v run/ss1 i th1 sgnd freqset fcb sw2 bg2 sense2 + sense2 stbymd v osense2 tg2 boost2 run/ss2 i th2 3.3v out 17 19 14 13 20 12 15 11 10 6 16 18 180 f 4v l2 4.6 h 10m + v out2 3.3v 5a v in 7v to 20v 63.4k 1% 20k 1% 10 f 6.3v 100pf 47pf 0.1 f 33k 10 10 10 330pf 180pf 0.1 f 5v enable 33k 330pf 0.1 f 3.3v enable 0.1 f stdby3.3v 0.01 f stdbymd 180pf vid1 vid1 15 vid2 vid2 16 vid3 vid3 17 vid4 vid4 18 + d5 mbrd 835l complete 2-step notebook power supply

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